TTTC: IOLTS 2011 Call for Participation - Registration Deadline June 12th!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

Issues related to on-line testing are increasingly important in modern electronic systems. In particular, the huge complexity of electronic systems has led to growth in reliability needs in several application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective on-line testing techniques. These needs have increased dramatically with the introduction of very deep submicron and nanometer technologies which adversely impact noise margins, process, voltage and temperature variations, aging and wearout and make integrating on-line testing and fault tolerance mandatory in many modern ICs. The International On-Line Testing Symposium (IOLTS) is an established forum for presenting novel ideas and experimental data on these areas. The symposium also emphasizes on-line testing in the continuous operation of large applications such as wired, cellular and satellite telecommunication, as well as in secure chips. The Symposium is sponsored by the IEEE Computer Society Test Technology Technical Council and organized by University of Athens and TIMA Laboratory.

Key Dates

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Symposium Registration Deadline: June 12th, 2011
Hotel Reservation Deadline: June 26, 2011

The Venue

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The 17th IEEE International On-Line Testing Symposium will be held in the Metropolitan hotel in Athens. Metropolital Hotel with its unique cosmopolitan atmosphere, combines traditional hospitality and luxury in central Athens. With a view to both the Acropolis and the Aegean Sea, the fully renovated Metropolitan hotel is ideally situated in front of the Faleron Olympic Coastal Park for both leisure and business travelers. The Metropolitan Hotel offers contemporary amenities in a relaxed and friendly atmosphere combined with traditional hospitality and impeccable service. Among these amenities, a free shuttle bus from/to Athens centre is included.

Workshop Registration

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The registration deadline is June 12th, 2011! You may register at:

http://tima.imag.fr/conferences/iolts/iolts11/registration.html

Advance Program

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Wednesday -- Thursday -- Friday

July 13, 2011 (Wednesday)

07:30 – 09:00: Symposium Registration

09:00 AM - 10:00 AM	OPENING SESSION
09:00 - 09:15	Welcome Message M.Nicolaidis (TIMA Lab), A.Paschalis (U Athens), General Chairs D.Gizopoulos (U Athens), X.Vera (Intel Barcelona Research Center), Program Chairs
09:15 – 10:00	Keynote: Prof. Babak Falsafi (EPFL)

10:00 AM – 10:15 AM BREAK

10:15 AM - 11:15 AM	Session 1 - Degradation Modeling and Transients Tolerance
1.1	Modeling and Mitigating NBTI in Nanoscaled Circuits S.Khan, S.Hamdioui (TU Delft)
1.2	Investigation of Multi Cell Upset in Sequential Logic and Validity on Triple Modular Redundancy T.Uemura, H.Matsuyama (Fujitsu)
1.3	High-Level Synthesis for Multi-Cycle Transient Fault Tolerant Datapaths T.Inoue, H.Henmi, Y.Yoshikawa, H.Ichihara (Hiroshima City University)

11:15 AM - 11:30 AM BREAK

11:30 AM - 12:30 PM	Session 2 - Faults in Real-Time Systems
2.1	An Intellectual Property Core to Detect Task Schedulling-Related Faults in RTOS-Based Embedded Systems D.Silva, L.Bolzani, F.Vargas (Catholic University - PUCRS)
2.2	RVC-Based Time-Predictable Faulty Caches for Safety-Critical Systems J.Abella, E.Quiñones, F.Cazorla, M.Valero (Barcelona Supercomputing Center), Y.Sazeides (U Cyprus)
2.3	Towards Functional-Safe Timing-Dependable Real-Time Architectures M.Paolieri (Barcelona Supercomputing Center), R.Mariani (YOGITECH)

12:30 AM - 1:30 PM LUNCH

1:30 PM - 2:30 PM	Session 3 - Fault Tolerance
3.1	Matrix Control-Flow Algorithm-Based Fault Tolerance R.Ferreira, A.Moreira, L.Carro (Universidade Federal do Rio Grande do Sul)
3.2	Selective Fault Tolerance for Finite State Machines M.Augustin (BTU Cottbus), M.Goessel (U Potsdam), R.Kraemer (IHP)
3.3	A New IP Core for Fast Error Detection and Fault Tolerance in COTS-based Solid State Mass Memories E.Costenaro, M.Violante (Politecnico di Torino), D.Alexandrescu (iRoC)

2:30 PM - 2:45 PM BREAK

2:45 PM - 3:45 PM	Session 4 - Variability and Degradation Tolerance in Multicores
4.1	Variability-aware Task Mapping Strategies for Many-core Processor Chips F.Chaix, G.Bizot, M.Nicolaidis, N.Zergainoh (TIMA Laboratory)
4.2	On Graceful Degradation of Microprocessors in Presence of Faults via Resource Banking R.Rodrigues, S.Kundu (U Massachusetts at Amherst)
4.3	On Graceful Degradation of Chip Multiprocessors in Presence of Faults via Flexible Pooling of Critical Execution Units R.Rodrigues, S.Kundu (U Massachusetts at Amherst)

3:45 PM - 4:00 PM COFFEE BREAK

4:00 PM - 5:00 PM	Session 5 - Memory BIST
5.1	A Multi-Objective Optimization for Memory BIST Sharing using a Genetic Algorithm Y.Kieffer (G-Scop Lab), L.Zaourar (LIP6 Lab), A.Wenzel (ST)
5.2	Memory BIST with Address Programmability M.Nicolaidis, A.Fradi, L.Anghel (TIMA Laboratory)
5.3	Generic BIST Architecture for Testing of Content Addressable Memories H.Grigoryan, G.Harutyunyan, S.Shoukourian, V.Vardanian, Y.Zorian (Synopsys)

5:00 PM - 5:15 PM BREAK

5:15 PM - 6:15 PM	Session 6 - Reliability Evaluation
6.1	A Reliable Fault Classifier for Dependable Systems on SRAM-based FPGAs C.Sandionigi, C.Bolchini (Politecnico di Milano)
6.2	An Approach to Reduce Computational Cost in Combinatorial Logic Netlist Reliability Analysis using Circuit Clustering and Conditional Probabilities J.Torras Flaquer, J.Marc Daveau (ST Microelectronics), L.Naviner (GET/ENST-CNRS/LTCI), P.Roche (ST Microelectronics)
6.3	Estimation of Component Criticality in Early Design Steps M.Sauer (U Freiburg), A.Czutro (U Freiburg), I.Polian (U Passau), B.Becker (U Freiburg)

6:15 PM - 6:30 PM BREAK

6:30 PM - 7:30 PM	Special Session 1

8:00 PM WELCOME RECEPTION

July 14, 2011 (Thursday)

9:00 AM - 10:00 AM	Session 7 - Testing and Error Tolerance for Low Power
7.1	A BIST Solution for Testing and Repair of Multi-Mode Power Switches Z.Zhang (Duke U), X.Kavousianos (U Ioannina), Y.Tsiatouhas (U Ioannina), K.Chakrabarty (Duke U)
7.2	Internal Model Control for a Self-Tuning Delay-Locked Loop in UWB Communication Systems R.Alhakim (TIMA Lab), E.Simeu (TIMA Lab), K.Raoof (GIPSA-LAB)
7.3	Real Time Cross-Layer Adaptation for Minimum Energy Wireless Image Transport using Bit Error Rate Control J.Natarajan, S.Sen, A.Chatterjee (Georgia Institute of Technology)

10:00 AM – 10:15 AM BREAK

10:15 AM - 11:15 AM	Special Session 2 - Security Concerns in Modern Integrated Circuits Organizer: Y.Makris (Yale U) Moderators: Y.Makris (Yale U), A.Veneris (U Toronto)
S2.1	The Cost of Cryptography in Hardware I.Verbauwhede, K. U. Leuven
S2.2	Countermeasures against Fault Attacks: the Good, the Bad, and the Ugly P.Maistri, R.Leveugle, TIMA Laboratory
S2.3	The Rise of Hardware Trojans B.Sunar, Worcester Polytechnic Institute

11:15 AM - 11:30 AM COFFEE BREAK

11:30 AM - 12:30 PM	Session 8 - Error Tolerant SRAM Designs
8.1	A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS Y.Shiyanovskii, A.Rajendran, C.Papachristou (Case Western Reserve U)
8.2	Noise Margin, Critical Charge and Power-Delay Tradeoffs for SRAM Design Space Exploration A Rajendran, Y.Shiyanovskii, F.Wolff, C.Papachristou (Case Western Reserve U)
8.3	Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure S.Yoshimoto (Kobe U), T.Amashita (Kobe U), D.Kozuwa (Kyushu U), T.Takata (Kyushu U), M.Yoshimura (Kyushu U), Y.Matsunaga (Kyushu U), H.Yasuura (Kyushu U), H.Kawaguchi (Kobe U), M.Yoshimoto (Kobe U)

12:30 AM - 1:30 PM LUNCH

1:30 PM - 2:30 PM	Session 9 - Error Correction
9.1	Error Correction Encoding for Multi-threshold Capture Mechanism K.Karmarkar, S.Tragoudas (Southern Illinois U)
9.2	Reduced Overhead Soft Error Mitigation Methodology Using Error Control Coding Techniques P.V (TI India), V.Singh (Indian Institute of Science), R.Parekhji (TI India)
9.3	Soft Error Correction in Embedded Storage Elements M.Imhof, H.-J.Wunderlich (U Stuttgart)

2:30 PM - 3:30 PM	Session 10 - Posters
10.1	A Comprehensive Soft Error Analysis Methodology for SoCs/ASICs Memory Instances D.Alexandrescu (iRoC)
10.2	A Novel Sensor for Aging Detection L.Yan, H.Liang, Z.Huang, Y.Liu (Hefei U of Technology, China)
10.3	A Verification Strategy for Fault-Detection and Fault-Tolerance Circuits G.Boschi, R.Mariani, S.Lorenzini (Yogitech)
10.4	Accelerating Secure Circuit Design of Diehard Battery of Tests of Randomness with Hardware Implementation A.Vaskova, C.Lopez-Ongil, L.Entrena, E.San Millan, A.Jimenez Horas (Carlos III U of Madrid)
10.5	An FPGA-Based Framework for Run-time Injection and Analysis of Soft Errors in Microprocessors M.Sauer, V.Tomashevich, J.Mueller, M.Lewis, A.Spilla, I.Polian, B.Becker, W.Burgard (U Freiburg and U Passau)
10.6	An On-Line Memory State Validation Using Shadow Memory Cloning M.Baklashov (Intel)
10.7	Control-Flow Error Recovery Using Commodity Multi-core Architecture Features N.Khoshavi, H.Zarandi, M.Maghsoudloo (Amirkabir U of Technology)
10.8	Detection of Trojan HW by Using Hidden Information on the System O.Keren (Bar Ilan U), I.Levin (Tel Aviv U), V.Sinelnikov (Bar Ilan U)
10.9	Fault Attack Resistant Deterministic Random Bit Generator usable for Key Randomization E.Boehl, P.Duplys (Robert Bosch GmbH)
10.10	Fault-Tolerance Assessment and Enhancement in SoCWire Interface: A System-On-Chip Wire R.Salamat, H.Zarandi (Amirkabir U of Technology)
10.11	Generalized Parity-Check Matrices for SEC-DED Codes with Fixed Parity V.Gherman, S.Evain, N.Seymour, Y.Bonhomme
10.12	ICT: Interface Software for the Characterization and Test of Mixed-Signal Power Cores J.Esteves (IST - UTL), T.Moita (INESC-ID), C.Almeida (IST-UTL /INESC-ID), M.Santos (IST/INESC-ID)
10.13	Loopback Output Router for reliable Network on Chip reliability C.Killian (LICM), C.Tanougast (LICM), F.Monteiro (U Paul Verlaine - Metz), A.Dandache (U Metz)
10.14	Multi-Level Secure JTAG Architecture L.Pierce U), S.Tragoudas (Southern Illinois U)
10.15	Self-Checking Test Circuits for Latches and Flip-Flops R.Ribas, Y.Sun, A.Reis (U Federal do Rio Grande do Sul), A.Ivanov (U of British Columbia)
10.16	Software-based Control Flow Error Detection and Correction Using Branch Triplication N.Farhady Ghalaty, S.Ghassem Miremadi, M.Fazeli, H.Izadirad (Sharif U of Technology)
10.17	Variations of Fault Manifestation during Burn-In - A Case Study on Industrial SRAM Test Results M.Linder (U of Applied Sciences Augsburg), A.Eder (U of Applied Sciences Augsburg), K.Oberländer (Infineon), M.Huch (Infineon)

4:00 PM - SOCIAL EVENT (Tour and Dinner)

July 15, 2011 (Friday)

9:00 AM - 10:00 AM	Session 11 - Security
11.1	A Side Channel Attack Countermeasure using System-On-Chip Power Profile Scrambling A.Krieg, J.Grinschgl, C.Steger, R.Weiss (Graz U of Technology), J.Haid (Infineon)
11.2	AKARI-X: a Pseudorandom Number Generator for Secure Lightweight Systems E.San Millan, H.Martin Gonzalez (U Carlos III of Madrid), P.Peris Lopez (TU Delft)
11.3	Algebraic Manipulation Detection Codes and Their Applications for Design of Secure Cryptographic Devices Z.Wang, M.Karpovsky (Boston U)

10:00 AM – 10:15 AM BREAK

10:15 AM - 11:15 AM	Special Session 3 - Safety Critical Systems: Reliability and Survivability Organizers/Moderators: J.Abella (Barelona Supercomputing Center), D.Gizopoulos (U Athens)
S3.1	Mission-critical and safety-critical systems: the challenges of the reliability and the survivability from an industrial perspective A.Grasset, S.Yehia, P.Bonnot (Thales)
S3.2	A Cost-effective Migration from Fault Detection to Fault Tolerance in Safety-Critical Systems R.Mariani (Yogitech)
S3.3	TBD

11:15 AM - 11:30 AM COFFEE BREAK

11:30 AM - 12:30 PM	Session 12 - Dependability Evaluation
12.1	A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits T.Takata, Y.Matsunaga (Kyushu U)
12.2	An Analytical Model for the Calculation of the Expected Miss Ratio in Faulty Caches D.Sanchez (U Murcia), Y.Sazeides (U Cyprus), J.Aragon (U Murcia), J.M.Garcia (U Murcia)
12.3	Evaluation Techniques for On-line Testing of Robust Systems Based on Critical Tasks Distribution A.Vaskova, C.Lopez-Ongil, M.Garcia Valderas, M.Portela-Garcia, L.Entrena (Carlos III U of Madrid)

12:30 AM - 1:30 PM LUNCH

1:30 PM - 2:30 PM	Session 13 - Errors in DRAMs, Microprocessors, and SoCs
13.1	Unidirectional Error Detection, Localization and Correction for DRAMs: Application to On-Line DRAM Repair Strategies M.Neagu (TU of Cluj-Napoca), L.Miclea (TU of Cluj-Napoca), J.Figueras (UPC)
13.2	An Effective Methodology for On-line Testing of Embedded Microprocessors P.Bernardi, L.Ciganda, E.Sanchez, M.Sonza Reorda (Politecnico Di Torino)
13.3	Fail-Safety in Core-Based System Design R.Baranowski, H.-J.Wunderlich (U Stuttgart)

2:30 PM	Symposium Closing Remarks

More Information

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Submission Information		General Information
Dimitris Gizopoulos	Xavier Vera	Michael Nicolaidis	Antonis Paschalis
University of Piraeus Department of Informatics Piraeus, Greece Tel: +30 210 414 2372 dgizop@unipi.gr	Intel Barcelona Research Center Intel Labs Barcelona Barcelona, Spain Tel: +34938001020 xavier.vera@intel.com	TIMA Laboratory Grenoble, France Tel: +33 (0) 4 76 57 46 96 michael.nicolaidis@imag.fr	University of Athens Dept. of Informatics & Telecomm. Athens, Greece Tel: +30 210 727 5231 paschali@di.uoa.gr

Committees

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Organizing Committee

General Chairs
M. Nicolaidis, TIMA Laboratory
A. Paschalis, U. Athens

Program Chairs
D. Gizopoulos , U. Athens
X. Vera, Intel

Special Sessions
R. Aitken, ARM
Y. Makris, Yale U.

Local Arrangements
G. Theodorou, U. Athens
T. Gatsos, U. Athens

Publications
M. Psarakis, U. Piraeus
N. Zergainoh, TIMA Laboratory

Publicity
L. Anghel, TIMA Laboratory
R. Velazco, TIMA Laboratory

Vice-General Chairs
Y. Zorian, Virage Logic
A. Chaterjee, Georgia Tech.

Vice-Program Chairs
S. Chakravarty, LSI Logic
M. Abadir, Freescale

Finance Chair
N. Kranitis, U. Athens

Audio Visual Chair
N. Foutris, U. Athens
V. Dimitsas, U. Athens

ETTTC Liaison
M. Sonza Reorda, Politec. di Torino

Program Committee

J. Abella, Barcelona Supercomp. Center
J. Abraham, U. Texas at Austin
D. Alexandrescu, iRoC
D. Appello, ST Microelectronics
M. Baklashov, ARM
R. Baumann, TI
M. Benabdenbi, LIP6
N. Bidokhti, Cisco
E. Boehl, Robert Bosch GmbH
N. Buard, EADS
A. Bystrov, U. Newcastle
R. Canal, UPC
Y. Cao, Arizona State U.
L. Carro, UFRGS
V. Chandra, ARM
M. De Alba, Intel
G. Di Natale, LIRMM
P. Fouillat, IXL-ENSEIRB
G. Georgakos, Infineon
P. Girard, LIRMM
M. Goessel, U. Postdam
W. Gustin, Infineon
A. Haggag, Freescale
J. Hayes, U. Michigan
T. Heijmen, NXP
S. Hellebrand, U. Paderborn
E. Ibe, Hitachi
A. Ivanov, U. Brit. Columbia
R. Iyer, U. Illinois
A. Krasniewski, Warsaw U.T.
R. Kumar, U. Illinois
S. Kundu, U. Mass. Amherst
R. Leveugle, TIMA
C. Lopez Ongil, U. Carlos III de Madrid
M. Lubaszewski, UFRGS
A. Majumdar, AMD/ATI
C. Metra, U. Bologna

M. Michael, U. Cyprus
M. Miranda, IMEC
S. Mitra, Stanford U.
F. Monteiro, U. Metz
S. Mukhopadhyaya, Georgia Tech.
D. Nikolos, U. Patras
M. Ottavi, U. Roma
P. Pande, Washington State U.
C. Papachristou, CWRU
R. Parekhji, TI
I. Parulkar, Cisco
Z. Peng, Linkoping U.
S. Piestrak, U. Metz
I. Polian, U. Passau
D. Pradhan, U. Bristol
P. Prinetto, Politec. di Torino
H. Puchner, Cypress
M. Rebaudengo, Politec. di Torino
K. Roy, Purdue U.
J. Segura, U. Illes Balears
N. Seifert, Intel
J. Semiao, INESC-ID / U. Algarve
E. Simeu, TIMA Laboratory
A. Singh, Auburn U.
V. Singh, IISc
C. Slayman, Sun
H. Stratigopoulos, TIMA
J.-P. Teixeira, IST/INESC-ID
N. Touba, U. Texas
S. Tragoudas, U. Southern Illinois
T. Uemura, Fujitsu Labs
F. Vargas, PUCRS
M. Violante, Politec. di Torino
I. Voyiatzis, TEI Athens
L.-C. Wang, U. C. Santa Barbara
H. J. Wunderlich, U. Stuttgart
Q. Xu, Chinese U. Hong Kong

For more information, visit us on the web at: http://tima.imag.fr/conferences/iolts

The 17th IEEE International On-Line Testing Symposium(IOLTS 2011 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).